The Intel MCS-51 (commonly termed 8051) is an internally Harvard architecture, complex instruction set computer (CISC) instruction set, single chip microcontroller (µC) series developed by Intel in 1980 for use in embedded systems. Intel’s original versions were popular in the 1980s and early 1990s and enhanced binary compatible derivatives remain popular today.
Intel’s original MCS-51 family was developed using N-type metal-oxide-semiconductor (NMOS) technology like its predecessor Intel MCS-48, but later versions, identified by a letter C in their name (e.g., 80C51) used complementary metal–oxide–semiconductor (CMOS) technology and consume less power than their NMOS predecessors. This made them more suitable for battery-powered devices.
The family was continued in 1996 with the enhanced 8-bit MCS-151 and the 8/16/32-bit MCS-251 family of binary compatible microcontrollers. While Intel no longer manufactures the MCS-51, MCS-151 and MCS-251 family, enhanced binary compatible derivatives made by numerous vendors remain popular today. Some derivatives integrate a digital signal processor (DSP). Beyond these physical devices, several companies also offer MCS-51 derivatives as IP cores for use in field-programmable gate array (FPGA) or application-specific integrated circuit (ASIC) designs.
The 8051 architecture provides many functions (central processing unit (CPU), random access memory (RAM), read-only memory (ROM), input/output (I/O), interrupt logic, timer, etc.) in one package:
- 8-bit arithmetic logic unit (ALU) and accumulator, 8-bit registers (one 16-bit register with special move instructions), 8-bit data bus and 2×16-bit address bus/program counter/data pointer and related 8/11/16-bit operations; hence it is mainly an 8-bit microcontroller
- Boolean processor with 17 instructions, 1-bit accumulator, 32 registers (4 bit-addressable 8-bit) and up to 144 special 1 bit-addressable RAM variables (18 bit-addressable 8-bit)
- Multiply, divide and compare instructions
- 4 fast switchable register banks with 8 registers each (memory mapped)
- Fast interrupt with optional register bank switching
- Interrupts and threads with selectable priority
- Dual 16-bit address bus – It can access 2 x 216 memory locations – 64 KB (65,536 locations) each of RAM and ROM
- 128 bytes of on-chip RAM (IRAM)
- 4 KiB of on-chip ROM, with a 16-bit (64 KiB) address space (PMEM). Not included on 803X variants
- Four 8-bit bi-directional input/output port, bit addressable
- UART (serial port)
- Two 16-bit Counter/timers
- Power saving mode (on some derivatives)
One feature of the 8051 core is the inclusion of a boolean processing engine which allows bit-level boolean logic operations to be carried out directly and efficiently on select internal registers, ports and select RAM locations. This feature helped cement the 8051’s popularity in industrial control applications because it reduced code size by as much as 30%. Another feature is the inclusion of four bank selectable working register sets which greatly reduce the amount of time required to complete an interrupt service routine. With one instruction, the 8051 can switch register banks versus the time consuming task of transferring the critical registers to the stack, or designated RAM locations. These registers also allowed the 8051 to quickly perform a context switch.
Once a UART, and a timer if necessary, has been configured, the programmer needs only write a simple interrupt routine to refill the send shift register whenever the last bit is shifted out by the UART and/or empty the full receive shift register (copy the data somewhere else). The main program then performs serial reads and writes simply by reading and writing 8-bit data to stacks.